Advanced Interconnect Protocols Using High-performance Deadlock-free Id Assignment

In a latest network-on-chip design, several cores and intellectual properties can be integrated into a one chip. For high-performance interconnects, designers rapidly adopt advance interconnect protocols that support mechanisms of parallel accessing, including outstanding transactions and out-of-order complete of transactions. To produce these novel mechanisms, a master tag an ID to each transaction to decide in-order or out-of-order properties. These advanced protocols may lead to transaction deadlocks that do not occur in existing protocols. To prevent the deadlock problem, current solutions stall suspicious transactions and in some cases, many such stalls can incur serious performance penalty. Here, we propose a novel ID assignment mechanism that guarantee the issue transactions to be deadlock-free and results in rapid reduction in the number of transaction stalls issued by masters. Our experiment results show great performance improvements compared with last works with little hardware and power overheads.